TY - JOUR
T1 - A Novel ΔΣ Control System Processor and Its VLSI Implementation
AU - Wu, Xiaofeng
AU - Chouliaras, Vassilios A.
AU - Nunez-Yanez, Jose Luis
AU - Goodall, Roger M.
PY - 2008/3
Y1 - 2008/3
N2 - This paper describes a novel control system processor architecture based on ΔΣ modulation known as the ΔΣ-CSP. The ΔΣ-CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of ΔΣ-CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-μm CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the ΔΣ-CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.
AB - This paper describes a novel control system processor architecture based on ΔΣ modulation known as the ΔΣ-CSP. The ΔΣ-CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of ΔΣ-CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-μm CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the ΔΣ-CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.
KW - 1-bit processing ΔΣ modulation
KW - Control system processor
KW - System-on-chip (SoC)
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=39749176239&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2007.915396
DO - 10.1109/TVLSI.2007.915396
M3 - Article
AN - SCOPUS:39749176239
VL - 16
SP - 217
EP - 228
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 3
ER -