A novel processor architecture for real-time control

Wu Xiaofeng, Vassilios Chouliaras, Jose Nunez-Yanez, Roger Goodall, Tanya Vladimirova

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)


This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.

Original languageEnglish
Title of host publicationAdvances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
PublisherSpringer Verlag
Number of pages11
ISBN (Print)3540400567, 9783540400561
Publication statusPublished - Sep 2006
Externally publishedYes
Event11th Asia-Pacific Conference on Advances in Computer Systems Architecture - Shanghai, China
Duration: 6 Sep 20068 Sep 2006
Conference number: 11

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4186 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference11th Asia-Pacific Conference on Advances in Computer Systems Architecture
Abbreviated titleACSAC 2006
Internet address


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