A novel processor architecture for real-time control

Wu Xiaofeng; Vassilios Chouliaras; Jose Nunez-Yanez; Roger Goodall; Tanya Vladimirova

A novel processor architecture for real-time control

Wu Xiaofeng, Vassilios Chouliaras, Jose Nunez-Yanez, Roger Goodall, Tanya Vladimirova

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.

Original language	English
Title of host publication	Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings
Publisher	Springer Verlag
Pages	270-280
Number of pages	11
ISBN (Print)	3540400567, 9783540400561
Publication status	Published - Sep 2006
Externally published	Yes
Event	11th Asia-Pacific Conference on Advances in Computer Systems Architecture - Shanghai, China Duration: 6 Sep 2006 → 8 Sep 2006 Conference number: 11 https://www.springer.com/gp/book/9783540400561

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	4186 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Conference

Conference	11th Asia-Pacific Conference on Advances in Computer Systems Architecture
Abbreviated title	ACSAC 2006
Country/Territory	China
City	Shanghai
Period	6/09/06 → 8/09/06
Internet address	https://www.springer.com/gp/book/9783540400561

Cite this

Xiaofeng, W., Chouliaras, V., Nunez-Yanez, J., Goodall, R., & Vladimirova, T. (2006). A novel processor architecture for real-time control. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings (pp. 270-280). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS). Springer Verlag.

Xiaofeng, Wu ; Chouliaras, Vassilios ; Nunez-Yanez, Jose et al. / A novel processor architecture for real-time control. Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Springer Verlag, 2006. pp. 270-280 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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title = "A novel processor architecture for real-time control",

abstract = "This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.",

author = "Wu Xiaofeng and Vassilios Chouliaras and Jose Nunez-Yanez and Roger Goodall and Tanya Vladimirova",

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booktitle = "Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings",

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Xiaofeng, W, Chouliaras, V, Nunez-Yanez, J, Goodall, R & Vladimirova, T 2006, A novel processor architecture for real-time control. in Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 4186 LNCS, Springer Verlag, pp. 270-280, 11th Asia-Pacific Conference on Advances in Computer Systems Architecture, Shanghai, China, 6/09/06.

A novel processor architecture for real-time control. / Xiaofeng, Wu; Chouliaras, Vassilios; Nunez-Yanez, Jose et al.

Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Springer Verlag, 2006. p. 270-280 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 4186 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.

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Xiaofeng W, Chouliaras V, Nunez-Yanez J, Goodall R, Vladimirova T. A novel processor architecture for real-time control. In Advances in Computer Systems Architecture - 11th Asia-Pacific Conference, ACSAC 2006, Proceedings. Springer Verlag. 2006. p. 270-280. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

A novel processor architecture for real-time control

Abstract

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