A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

C. F. Tsang, C. K. Chang, A. Krishnamoorthy, K. Y. Ee, Y. J. Su, H. Y. Li, W. H. Li, L. Y. Wong

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.

LanguageEnglish
Pages517-525
Number of pages9
JournalMicroelectronics Reliability
Volume45
Issue number3-4
Early online date11 Sep 2004
DOIs
Publication statusPublished - 1 Mar 2005
Externally publishedYes

Fingerprint

Chemical vapor deposition
vapor deposition
Processing
Metallizing
Electric breakdown
Fluorides
caps
acceptability
cleaning
sprayers
fluorides
Seed
seeds
Etching
Cleaning
Capacitance
breakdown
capacitance
Metals
etching

Cite this

Tsang, C. F., Chang, C. K., Krishnamoorthy, A., Ee, K. Y., Su, Y. J., Li, H. Y., ... Wong, L. Y. (2005). A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections. Microelectronics Reliability, 45(3-4), 517-525. https://doi.org/10.1016/j.microrel.2004.07.007
Tsang, C. F. ; Chang, C. K. ; Krishnamoorthy, A. ; Ee, K. Y. ; Su, Y. J. ; Li, H. Y. ; Li, W. H. ; Wong, L. Y. / A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections. In: Microelectronics Reliability. 2005 ; Vol. 45, No. 3-4. pp. 517-525.
@article{f05d25c637a34485bf8cbc4bd0c0c876,
title = "A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections",
abstract = "Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.",
author = "Tsang, {C. F.} and Chang, {C. K.} and A. Krishnamoorthy and Ee, {K. Y.} and Su, {Y. J.} and Li, {H. Y.} and Li, {W. H.} and Wong, {L. Y.}",
year = "2005",
month = "3",
day = "1",
doi = "10.1016/j.microrel.2004.07.007",
language = "English",
volume = "45",
pages = "517--525",
journal = "Microelectronics Reliability",
issn = "0026-2714",
publisher = "Elsevier Limited",
number = "3-4",

}

Tsang, CF, Chang, CK, Krishnamoorthy, A, Ee, KY, Su, YJ, Li, HY, Li, WH & Wong, LY 2005, 'A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections', Microelectronics Reliability, vol. 45, no. 3-4, pp. 517-525. https://doi.org/10.1016/j.microrel.2004.07.007

A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections. / Tsang, C. F.; Chang, C. K.; Krishnamoorthy, A.; Ee, K. Y.; Su, Y. J.; Li, H. Y.; Li, W. H.; Wong, L. Y.

In: Microelectronics Reliability, Vol. 45, No. 3-4, 01.03.2005, p. 517-525.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A study of post-etch wet clean on electrical and reliability performance of Cu/low k interconnections

AU - Tsang, C. F.

AU - Chang, C. K.

AU - Krishnamoorthy, A.

AU - Ee, K. Y.

AU - Su, Y. J.

AU - Li, H. Y.

AU - Li, W. H.

AU - Wong, L. Y.

PY - 2005/3/1

Y1 - 2005/3/1

N2 - Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.

AB - Integration of Cu with low k dielectrics has gained wide acceptance for 130 nm and beyond technology nodes at back-end-of-line (BEOL) interconnection in order to reduce both the RC delay and parasitic capacitance. Wet clean is one of the critical steps to remove post plasma etch residues. In this paper, the impacts of wet clean process after etching of (a) via, (b) metal 2 trench and (c) Cu cap of dual damascene structure on electrical performance of 130 nm Cu/CVD low k SiOCH metallization were explored and discussed. Electrical yields and dielectric breakdown strength of interconnects from the use of batch spray and single wafer processing systems of wet clean were also compared. We observed that electrical yields of interconnects were considerably dependant on optimized processing conditions (temperature, time, and mega-sonic power) and appropriate wet clean chemistry. The use of fluoride-based mixture of wet clean chemical for all three post-etch clean is very effective in cleaning the via and trench line before Ta barrier/Cu seed deposition. As a result, we successfully integrated double level Cu/CVD low k BEOL interconnection with excellent electrical and reliability performance.

UR - http://www.scopus.com/inward/record.url?scp=15744368770&partnerID=8YFLogxK

U2 - 10.1016/j.microrel.2004.07.007

DO - 10.1016/j.microrel.2004.07.007

M3 - Article

VL - 45

SP - 517

EP - 525

JO - Microelectronics Reliability

T2 - Microelectronics Reliability

JF - Microelectronics Reliability

SN - 0026-2714

IS - 3-4

ER -