Advanced front-end processes for the 45 nm CMOS technology node

E. J.H. Collart, S. B. Felch, H. Graoui, D. Kirkwood, S. Tallavarjula, J. A. Van Den Berg, J. Hamilton, N. E.B. Cowern, K. J. Kirkby

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

The process development focus for 45 nm technology node is very firmly on the transistor and substrate. Formation of ultra-shallow, abrupt and well-activated extension regions remains one of the challenges. For p-type metal oxide semiconductor (PMOS) transistors, co-implantation of fluorine and boron in a pre-amorphised substrate can significantly improve the activation, abruptness and junction depth. Here, we show results of an optimisation study of both F and Ge energies, and of F dose. The process window for optimisation was found to be reasonably large. For n-type metal oxide semiconductor (NMOS) transistor, antimony has been investigated as an option for source/drain extension formation. This study shows that a 1 × 1015 cm -2, 5 keV antimony (Sb) implant under solid phase epitaxial regrowth conditions can meet the 45 nm node requirements. The damage evolution has also been studied in detail using medium energy ion mass spectroscopy (MEIS). On the anneal side, we report an optimisation study of Ge pre-amorphisation energies and doses for a 1 × 1015 cm-2, 500eV B implant using a scanning laser millisecond anneal technique and show that under the right conditions one can get very close to the 45 nm node requirements. Full melt laser thermal processing (LTP) is another option to achieve the required junctions. The activation, diffusion and de-activation behaviour of Sb under LTP conditions has been investigated. The effects of LTP on silicon-on-insulators (SOI) wafers have also been investigated for low energy arsenic implants. It was found that careful optimisation is required due to the different thermal response of the SOI substrate compared to bulk. Ultra-shallow junction formation on SOI wafers was further investigated for low energy boron implants (200 eV-5 keV) into different SOI thicknesses and an initial comparison between B and BF2 implants was performed. The regrowth rate of amorphous layers in bulk and SOI was measured as a function of B implant dose for 500 eV B implants.

Original languageEnglish
Pages (from-to)118-129
Number of pages12
JournalMaterials Science and Engineering B: Solid-State Materials for Advanced Technology
Volume114-115
Issue numberSPEC. ISS.
Early online date7 Oct 2004
DOIs
Publication statusPublished - 15 Dec 2004
Externally publishedYes

Fingerprint

Silicon
CMOS
insulators
silicon
Antimony
Transistors
optimization
Boron
transistors
Lasers
Chemical activation
antimony
metal oxide semiconductors
dosage
lasers
boron
Substrates
Metals
energy
wafers

Cite this

Collart, E. J.H. ; Felch, S. B. ; Graoui, H. ; Kirkwood, D. ; Tallavarjula, S. ; Van Den Berg, J. A. ; Hamilton, J. ; Cowern, N. E.B. ; Kirkby, K. J. / Advanced front-end processes for the 45 nm CMOS technology node. In: Materials Science and Engineering B: Solid-State Materials for Advanced Technology. 2004 ; Vol. 114-115, No. SPEC. ISS. pp. 118-129.
@article{a557c20e62b24d2a86fa45a832af0d43,
title = "Advanced front-end processes for the 45 nm CMOS technology node",
abstract = "The process development focus for 45 nm technology node is very firmly on the transistor and substrate. Formation of ultra-shallow, abrupt and well-activated extension regions remains one of the challenges. For p-type metal oxide semiconductor (PMOS) transistors, co-implantation of fluorine and boron in a pre-amorphised substrate can significantly improve the activation, abruptness and junction depth. Here, we show results of an optimisation study of both F and Ge energies, and of F dose. The process window for optimisation was found to be reasonably large. For n-type metal oxide semiconductor (NMOS) transistor, antimony has been investigated as an option for source/drain extension formation. This study shows that a 1 × 1015 cm -2, 5 keV antimony (Sb) implant under solid phase epitaxial regrowth conditions can meet the 45 nm node requirements. The damage evolution has also been studied in detail using medium energy ion mass spectroscopy (MEIS). On the anneal side, we report an optimisation study of Ge pre-amorphisation energies and doses for a 1 × 1015 cm-2, 500eV B implant using a scanning laser millisecond anneal technique and show that under the right conditions one can get very close to the 45 nm node requirements. Full melt laser thermal processing (LTP) is another option to achieve the required junctions. The activation, diffusion and de-activation behaviour of Sb under LTP conditions has been investigated. The effects of LTP on silicon-on-insulators (SOI) wafers have also been investigated for low energy arsenic implants. It was found that careful optimisation is required due to the different thermal response of the SOI substrate compared to bulk. Ultra-shallow junction formation on SOI wafers was further investigated for low energy boron implants (200 eV-5 keV) into different SOI thicknesses and an initial comparison between B and BF2 implants was performed. The regrowth rate of amorphous layers in bulk and SOI was measured as a function of B implant dose for 500 eV B implants.",
keywords = "45 nm technology node, PMOS, Silicon-on-insulators wafers",
author = "Collart, {E. J.H.} and Felch, {S. B.} and H. Graoui and D. Kirkwood and S. Tallavarjula and {Van Den Berg}, {J. A.} and J. Hamilton and Cowern, {N. E.B.} and Kirkby, {K. J.}",
year = "2004",
month = "12",
day = "15",
doi = "10.1016/j.mseb.2004.07.018",
language = "English",
volume = "114-115",
pages = "118--129",
journal = "Materials Science and Engineering B: Solid-State Materials for Advanced Technology",
issn = "0921-5107",
publisher = "Elsevier BV",
number = "SPEC. ISS.",

}

Collart, EJH, Felch, SB, Graoui, H, Kirkwood, D, Tallavarjula, S, Van Den Berg, JA, Hamilton, J, Cowern, NEB & Kirkby, KJ 2004, 'Advanced front-end processes for the 45 nm CMOS technology node', Materials Science and Engineering B: Solid-State Materials for Advanced Technology, vol. 114-115, no. SPEC. ISS., pp. 118-129. https://doi.org/10.1016/j.mseb.2004.07.018

Advanced front-end processes for the 45 nm CMOS technology node. / Collart, E. J.H.; Felch, S. B.; Graoui, H.; Kirkwood, D.; Tallavarjula, S.; Van Den Berg, J. A.; Hamilton, J.; Cowern, N. E.B.; Kirkby, K. J.

In: Materials Science and Engineering B: Solid-State Materials for Advanced Technology, Vol. 114-115, No. SPEC. ISS., 15.12.2004, p. 118-129.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Advanced front-end processes for the 45 nm CMOS technology node

AU - Collart, E. J.H.

AU - Felch, S. B.

AU - Graoui, H.

AU - Kirkwood, D.

AU - Tallavarjula, S.

AU - Van Den Berg, J. A.

AU - Hamilton, J.

AU - Cowern, N. E.B.

AU - Kirkby, K. J.

PY - 2004/12/15

Y1 - 2004/12/15

N2 - The process development focus for 45 nm technology node is very firmly on the transistor and substrate. Formation of ultra-shallow, abrupt and well-activated extension regions remains one of the challenges. For p-type metal oxide semiconductor (PMOS) transistors, co-implantation of fluorine and boron in a pre-amorphised substrate can significantly improve the activation, abruptness and junction depth. Here, we show results of an optimisation study of both F and Ge energies, and of F dose. The process window for optimisation was found to be reasonably large. For n-type metal oxide semiconductor (NMOS) transistor, antimony has been investigated as an option for source/drain extension formation. This study shows that a 1 × 1015 cm -2, 5 keV antimony (Sb) implant under solid phase epitaxial regrowth conditions can meet the 45 nm node requirements. The damage evolution has also been studied in detail using medium energy ion mass spectroscopy (MEIS). On the anneal side, we report an optimisation study of Ge pre-amorphisation energies and doses for a 1 × 1015 cm-2, 500eV B implant using a scanning laser millisecond anneal technique and show that under the right conditions one can get very close to the 45 nm node requirements. Full melt laser thermal processing (LTP) is another option to achieve the required junctions. The activation, diffusion and de-activation behaviour of Sb under LTP conditions has been investigated. The effects of LTP on silicon-on-insulators (SOI) wafers have also been investigated for low energy arsenic implants. It was found that careful optimisation is required due to the different thermal response of the SOI substrate compared to bulk. Ultra-shallow junction formation on SOI wafers was further investigated for low energy boron implants (200 eV-5 keV) into different SOI thicknesses and an initial comparison between B and BF2 implants was performed. The regrowth rate of amorphous layers in bulk and SOI was measured as a function of B implant dose for 500 eV B implants.

AB - The process development focus for 45 nm technology node is very firmly on the transistor and substrate. Formation of ultra-shallow, abrupt and well-activated extension regions remains one of the challenges. For p-type metal oxide semiconductor (PMOS) transistors, co-implantation of fluorine and boron in a pre-amorphised substrate can significantly improve the activation, abruptness and junction depth. Here, we show results of an optimisation study of both F and Ge energies, and of F dose. The process window for optimisation was found to be reasonably large. For n-type metal oxide semiconductor (NMOS) transistor, antimony has been investigated as an option for source/drain extension formation. This study shows that a 1 × 1015 cm -2, 5 keV antimony (Sb) implant under solid phase epitaxial regrowth conditions can meet the 45 nm node requirements. The damage evolution has also been studied in detail using medium energy ion mass spectroscopy (MEIS). On the anneal side, we report an optimisation study of Ge pre-amorphisation energies and doses for a 1 × 1015 cm-2, 500eV B implant using a scanning laser millisecond anneal technique and show that under the right conditions one can get very close to the 45 nm node requirements. Full melt laser thermal processing (LTP) is another option to achieve the required junctions. The activation, diffusion and de-activation behaviour of Sb under LTP conditions has been investigated. The effects of LTP on silicon-on-insulators (SOI) wafers have also been investigated for low energy arsenic implants. It was found that careful optimisation is required due to the different thermal response of the SOI substrate compared to bulk. Ultra-shallow junction formation on SOI wafers was further investigated for low energy boron implants (200 eV-5 keV) into different SOI thicknesses and an initial comparison between B and BF2 implants was performed. The regrowth rate of amorphous layers in bulk and SOI was measured as a function of B implant dose for 500 eV B implants.

KW - 45 nm technology node

KW - PMOS

KW - Silicon-on-insulators wafers

UR - http://www.scopus.com/inward/record.url?scp=10644254427&partnerID=8YFLogxK

U2 - 10.1016/j.mseb.2004.07.018

DO - 10.1016/j.mseb.2004.07.018

M3 - Article

VL - 114-115

SP - 118

EP - 129

JO - Materials Science and Engineering B: Solid-State Materials for Advanced Technology

JF - Materials Science and Engineering B: Solid-State Materials for Advanced Technology

SN - 0921-5107

IS - SPEC. ISS.

ER -