An analogue test response compaction technique using delta-sigma modulation

Sheikh Saine, Julian Raczkowycz, Peter Mather

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

An analogue and mixed-signal Built-In-Self-Test (BIST) scheme suitable for detecting manufacturing defects in embedded linear macros is presented. The BIST scheme uses a delta-sigma (ΔΣ) modulator and a binary counter to perform an analogue test response compaction technique. This technique produces a signature for a circuit under test, which relates to the amplitude and frequency of the analogue response. Fault simulations performed on a two-stage CMOS operational amplifier and a continuous-time state variable filter have shown that a fault coverage (>80%) is attainable. These simulation results suggest that the probability of any fault masking occurring using the proposed compression technique is insignificant.

Original languageEnglish
Pages (from-to)339-350
Number of pages12
JournalMicroelectronics Journal
Volume32
Issue number4
Early online date21 Mar 2001
DOIs
Publication statusPublished - 1 Apr 2001

Fingerprint

Delta sigma modulation
Built-in self test
self tests
Compaction
analogs
modulation
Operational amplifiers
Modulators
Macros
operational amplifiers
masking
Defects
Networks (circuits)
modulators
CMOS
counters
manufacturing
simulation
signatures
filters

Cite this

Saine, Sheikh ; Raczkowycz, Julian ; Mather, Peter. / An analogue test response compaction technique using delta-sigma modulation. In: Microelectronics Journal. 2001 ; Vol. 32, No. 4. pp. 339-350.
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An analogue test response compaction technique using delta-sigma modulation. / Saine, Sheikh; Raczkowycz, Julian; Mather, Peter.

In: Microelectronics Journal, Vol. 32, No. 4, 01.04.2001, p. 339-350.

Research output: Contribution to journalArticle

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