Architectures for high performance digital control processors

R. S Habib Istepanian, R. M. Goodall, S. R. Jones

Research output: Contribution to journalConference articlepeer-review


A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.

Original languageEnglish
Number of pages6
JournalIEE Colloquium (Digest)
Issue number116
Publication statusPublished - 1995
Externally publishedYes
EventIEE Electronics Division Colloquium on Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures - London, United Kingdom
Duration: 31 May 199531 May 1995


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