Architectures for high performance digital control processors

R. S Habib Istepanian, R. M. Goodall, S. R. Jones

Research output: Contribution to journalConference article

Abstract

A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.

Original languageEnglish
Number of pages6
JournalIEE Colloquium (Digest)
Issue number116
DOIs
Publication statusPublished - 1995
Externally publishedYes
EventIEE Electronics Division Colloquium on Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures - London, UK
Duration: 31 May 199531 May 1995

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Control systems

Cite this

@article{2e69df63eceb4daeb0bfdd0dc6fb77a5,
title = "Architectures for high performance digital control processors",
abstract = "A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.",
author = "Istepanian, {R. S Habib} and Goodall, {R. M.} and Jones, {S. R.}",
year = "1995",
doi = "10.1049/ic:19950780",
language = "English",
journal = "IEE Colloquium (Digest)",
issn = "0963-3308",
publisher = "Institute of Electrical Engineers",
number = "116",

}

Architectures for high performance digital control processors. / Istepanian, R. S Habib; Goodall, R. M.; Jones, S. R.

In: IEE Colloquium (Digest), No. 116, 1995.

Research output: Contribution to journalConference article

TY - JOUR

T1 - Architectures for high performance digital control processors

AU - Istepanian, R. S Habib

AU - Goodall, R. M.

AU - Jones, S. R.

PY - 1995

Y1 - 1995

N2 - A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.

AB - A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.

UR - http://www.scopus.com/inward/record.url?scp=0029212160&partnerID=8YFLogxK

U2 - 10.1049/ic:19950780

DO - 10.1049/ic:19950780

M3 - Conference article

JO - IEE Colloquium (Digest)

JF - IEE Colloquium (Digest)

SN - 0963-3308

IS - 116

ER -