Architectures for high performance digital control processors

A research project focusing on the development of algorithms and architectures for a Control System Processor (CSP) is presented. The design considerations suggest how new processor architectures targeted generally for critical linear time invariant systems can be arranged to yield higher performance controllers than those designed in the classical fashion. This is based on the structuring of the complexity of the digital controllers and an assessment of their associated implementational and computational demands. An active suspension controller is used an example to illustrate some of the issues.