Auction Based Power Aware Real-Time Scheduler for Heterogeneous FPGA Cloud Platform

Atanu Majumder, Krishnendu Guha, Sangeet Saha, Amlan Chakrabarti

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Auction based scheduling strategies in current literature are essentially associated with software for cloud environments, as the underlying hardware is considered generic and not re-configurable at runtime. However, recent cloud infrastructures like Amazon EC2 F1 services and Microsoft Azure deploy field programmable gate arrays (FPGAs) as an integral component, for its property of dynamic re-configuration at runtime. Auction based scheduling strategies for FPGA based cloud platforms is still not explored, where the goal is to optimize power dissipation. In this work, we try to deploy an auction based power aware scheduling mechanism for real-time task scheduling in heterogeneous FPGA based cloud platforms, which we term 'Auction Based Power Aware Real-Time Scheduler' (AB-PARTS). In this mechanism, a local scheduler is invoked to execute requested tasks (periodic and non-periodic) to meet its real-time requirements. If tasks cannot be guaranteed execution in the local processing elements (PEs) or FPGAs, switch to a distributed scheduling approach with an auction scheme is made. In the auction scheme, task details are broadcasted to other schedulers, which send back an acknowledgment with reward value based on the dynamic status of the PEs of the schedulers. Task is dispatched to the scheduler, which generates the maximum reward value. The scheduler allocates the task to its PEs in such a manner so that the power consumption is optimized. For experimental purpose, we deploy a cloud platform with heterogeneous Altera FPGA boards, where performance of the proposed strategy is tested with standard tasks of the EPFL benchmark suite. Related results depict that the strategy is quite capable to achieve high resource utilization with low power consumption over different simulation scenarios.

Original languageEnglish
Title of host publicationProceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019
PublisherIEEE
Pages81-86
Number of pages6
ISBN (Electronic)9781728146553
ISBN (Print)9781728146560
DOIs
Publication statusPublished - 16 Dec 2019
Externally publishedYes
Event5th IEEE International Symposium on Smart Electronic Systems - Rourkela, India
Duration: 16 Dec 201918 Dec 2019
Conference number: 5

Conference

Conference5th IEEE International Symposium on Smart Electronic Systems
Abbreviated titleiSES 2019
Country/TerritoryIndia
CityRourkela
Period16/12/1918/12/19

Fingerprint

Dive into the research topics of 'Auction Based Power Aware Real-Time Scheduler for Heterogeneous FPGA Cloud Platform'. Together they form a unique fingerprint.

Cite this