Abstract
The SD-stacked IC (3D-SIC) approach of lMEC is based on the fabrication of through-wafer interconnects using front-end type processes, achieving a maximal die-to-die interconnect density of up to 104 interconnects/mm'. This approach interferes minimally with back-end interconnect capabilities, and allows to reroute interconnect lines through the die from any back-end of line (BEOL) metal layer. The present article reports on the Cu-Cu thermo-compression bonding of 5 /mi-diameter Cu nails to polished Cu blankets. The bond strength was assessed through die shear tests. Cu-Cu shear stress values of up to 100 MPa were measured. The impact of the bonding conditions (i.e. bonding temperature and force) on the bond strength was evaluated, while the shear stress was a posteriori correlated to the surface roughness of the Cu bonding substrates. Moreover, the effect of a pre-bonding etch process aiming at the elimination of the bond-compromising Cu oxides was investigated.
Original language | English |
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Title of host publication | Proceedings - 2006 International Symposium on Microelectronics, IMAPS 2006 |
Pages | 1252-1257 |
Number of pages | 6 |
Publication status | Published - 1 Dec 2006 |
Externally published | Yes |
Event | 39th International Symposium on Microelectronics - San Diego, United States Duration: 8 Oct 2006 → 12 Oct 2006 Conference number: 39 |
Conference
Conference | 39th International Symposium on Microelectronics |
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Abbreviated title | IMAPS2006 |
Country/Territory | United States |
City | San Diego |
Period | 8/10/06 → 12/10/06 |