Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Anju Johnson, Junxiu Liu, Alan Millard, Shvan Karim, Andy Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David Halliday

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on VLSI Design
PublisherIEEE
Pages49-54
Number of pages6
ISBN (Electronic)9781538636923
ISBN (Print)9781538636930
DOIs
Publication statusPublished - 29 Mar 2018
Externally publishedYes
Event31st International Conference on Very-Large-Scale Integration Design and 17th International Conference on Embedded Systems - Pune, India
Duration: 6 Jan 201810 Jan 2018
Conference number: 31
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8326586 (Link to Conference Proceedings)

Conference

Conference31st International Conference on Very-Large-Scale Integration Design and 17th International Conference on Embedded Systems
CountryIndia
CityPune
Period6/01/1810/01/18
Internet address

Fingerprint

Plasticity
Field programmable gate arrays (FPGA)
Neural networks
Neurons
Fault tolerance
Network performance
Robotics
Astrocytes

Cite this

Johnson, A., Liu, J., Millard, A., Karim, S., Tyrrell, A., Harkin, J., ... Halliday, D. (2018). Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. In Proceedings of the IEEE International Conference on VLSI Design (pp. 49-54). IEEE. https://doi.org/10.1109/VLSID.2018.36
Johnson, Anju ; Liu, Junxiu ; Millard, Alan ; Karim, Shvan ; Tyrrell, Andy ; Harkin, Jim ; Timmis, Jon ; McDaid, Liam ; Halliday, David. / Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. Proceedings of the IEEE International Conference on VLSI Design. IEEE, 2018. pp. 49-54
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abstract = "The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.",
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Johnson, A, Liu, J, Millard, A, Karim, S, Tyrrell, A, Harkin, J, Timmis, J, McDaid, L & Halliday, D 2018, Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. in Proceedings of the IEEE International Conference on VLSI Design. IEEE, pp. 49-54, 31st International Conference on Very-Large-Scale Integration Design and 17th International Conference on Embedded Systems, Pune, India, 6/01/18. https://doi.org/10.1109/VLSID.2018.36

Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. / Johnson, Anju; Liu, Junxiu; Millard, Alan; Karim, Shvan; Tyrrell, Andy ; Harkin, Jim; Timmis, Jon; McDaid, Liam; Halliday, David.

Proceedings of the IEEE International Conference on VLSI Design. IEEE, 2018. p. 49-54.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AB - The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of the proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

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Johnson A, Liu J, Millard A, Karim S, Tyrrell A, Harkin J et al. Fault-tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs. In Proceedings of the IEEE International Conference on VLSI Design. IEEE. 2018. p. 49-54 https://doi.org/10.1109/VLSID.2018.36