In this paper several fault tolerant strategies which can be implemented on nine switch inverter has been investigated. The developed strategies provide compensation for open circuit and short circuit failures on semiconductor devices. In addition unique post fault controls have been proposed for each strategy. The first applied topology is switch redundant topology and can tolerate all switch failures. The second one is a four leg topology which tolerates just open circuit fault. The third one called phase redundant topology can deliver rated power at all switch failures. Finally performance of all post fault topologies is verified by simulation results.
|Title of host publication
|2011 2nd Power Electronics, Drive Systems and Technologies Conference, PEDSTC 2011
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 5 Apr 2011
|2nd Power Electronics, Drive Systems and Technologies Conference - Tehran, Iran, Islamic Republic of
Duration: 16 Feb 2011 → 17 Feb 2011
Conference number: 2
|2nd Power Electronics, Drive Systems and Technologies Conference
|Iran, Islamic Republic of
|16/02/11 → 17/02/11