Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs

Anju Johnson, Junxiu Liu, Alan Millard, Shvan Karim, Andy Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David Halliday

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.
LanguageEnglish
Title of host publication2017 International Conference on Field Programmable Technology (ICFPT)
EditorsPaul Beckett, Ken Eguro, David Boland
PublisherIEEE
Pages195-198
Number of pages4
ISBN (Electronic)9781538626566
ISBN (Print)9781538626573
DOIs
Publication statusPublished - 5 Feb 2018
Externally publishedYes
EventInternational Conference on Field-Programmable Technology - Melbourne, Australia
Duration: 11 Dec 201713 Dec 2017
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8269417 (Link to Conference Proceedings)

Conference

ConferenceInternational Conference on Field-Programmable Technology
Abbreviated titleFPT 17
CountryAustralia
CityMelbourne
Period11/12/1713/12/17
Internet address

Fingerprint

Fault tolerance
Field programmable gate arrays (FPGA)
Repair
Neurons
Neural networks
Clocks
Hardware
Recovery
Tile
Brain
Electric power utilization
Astrocytes

Cite this

Johnson, A., Liu, J., Millard, A., Karim, S., Tyrrell, A., Harkin, J., ... Halliday, D. (2018). Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs. In P. Beckett, K. Eguro, & D. Boland (Eds.), 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 195-198). IEEE. https://doi.org/10.1109/FPT.2017.8280139
Johnson, Anju ; Liu, Junxiu ; Millard, Alan ; Karim, Shvan ; Tyrrell, Andy ; Harkin, Jim ; Timmis, Jon ; McDaid, Liam ; Halliday, David. / Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs. 2017 International Conference on Field Programmable Technology (ICFPT). editor / Paul Beckett ; Ken Eguro ; David Boland. IEEE, 2018. pp. 195-198
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Johnson, A, Liu, J, Millard, A, Karim, S, Tyrrell, A, Harkin, J, Timmis, J, McDaid, L & Halliday, D 2018, Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs. in P Beckett, K Eguro & D Boland (eds), 2017 International Conference on Field Programmable Technology (ICFPT). IEEE, pp. 195-198, International Conference on Field-Programmable Technology, Melbourne, Australia, 11/12/17. https://doi.org/10.1109/FPT.2017.8280139

Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs. / Johnson, Anju; Liu, Junxiu; Millard, Alan; Karim, Shvan; Tyrrell, Andy ; Harkin, Jim; Timmis, Jon; McDaid, Liam; Halliday, David.

2017 International Conference on Field Programmable Technology (ICFPT). ed. / Paul Beckett; Ken Eguro; David Boland. IEEE, 2018. p. 195-198.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Timmis, Jon

AU - McDaid, Liam

AU - Halliday, David

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N2 - We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

AB - We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. The system maintains effective functional behavior with a loss of up to 90% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware footprints with the repair unit which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the impact on power consumption of the design is also minimal (1.371W). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

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M3 - Conference contribution

SN - 9781538626573

SP - 195

EP - 198

BT - 2017 International Conference on Field Programmable Technology (ICFPT)

A2 - Beckett, Paul

A2 - Eguro, Ken

A2 - Boland, David

PB - IEEE

ER -

Johnson A, Liu J, Millard A, Karim S, Tyrrell A, Harkin J et al. Homeostatic Fault Tolerance in Spiking Neural Networks utilizing Dynamic Partial Reconfiguration of FPGAs. In Beckett P, Eguro K, Boland D, editors, 2017 International Conference on Field Programmable Technology (ICFPT). IEEE. 2018. p. 195-198 https://doi.org/10.1109/FPT.2017.8280139