Novel architecture of modular exponent on reconfigurable system

Rourab Paul, Sangeet Saha, Chandrajit Pal, Suman Sau

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Citations (Scopus)


This paper proposes a single chip solution of the modulus exponent operation for FPGA based embedded system applications. Throughput and resource usage are the two most important issues in the design of embedded systems and the designers must need to choose appropriate hardware architecture to meet these requirements. There are two ways of hardware design namely parallel architecture and sequential architecture. Though sequential architecture has lesser throughput it is suitable for limited resource hardware domain like FPGA based systems. Parallel design may consume huge resources but it has better throughput compare to its sequential counterpart. In this paper, we have proposed the design and implementation of modulus exponent operation in three different ways namely single clock architecture, sequential architecture and a processor core based architecture. The proposed design is implemented and verified on Spartan 3E (XC3S500E-FG320) and Virtex-5, (XC5VLX110T-FF1136) FPGA system. We have used VHDL and SystemC for the various implementations in our work. The results show that our design is better in terms of execution speed and hardware utilization in comparison with the existing research work.

Original languageEnglish
Title of host publication2012 Students Conference on Engineering and Systems, SCES 2012
Number of pages6
ISBN (Electronic)9781467304559, 9781467304542
ISBN (Print)9781467304566
Publication statusPublished - 14 May 2012
Externally publishedYes
Event2012 Students Conference on Engineering and Systems - Allahabad, Uttar Pradesh, India
Duration: 16 Mar 201218 Mar 2012


Conference2012 Students Conference on Engineering and Systems
Abbreviated titleSCES 2012
CityAllahabad, Uttar Pradesh


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