Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications

Anju Johnson, Sikhar Patranabis, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Citations (Scopus)


Many Internet of Things (IoT) applications can potentially benefit from the remote Dynamic Partial Reconfiguration (DPR) capabilities of modern Field Programmable Gate Arrays (FPGAs). Such capabilities enable changes in the circuit mapped on the FPGA, for modification or enhancement of functionality offered by the FPGA without taking it offline, via remote communications over a network. However, the use of remote DPR can result in security threats with catastrophic consequences. In this paper, we design two Hardware Trojan Horse attacks that exploit the remote DPR capability of the FPGA, on an encryption circuit and a true random number generator circuit, respectively. In particular, these attacks target the clock signal management circuitry on the FPGA to disrupt functionality. We substantiate the threat by demonstrating successful remote attacks via transfer of malicious bitstreams to a Virtex-5 FPGA, thereby embedding the HTH. Finally, we propose plausible countermeasures to prevent such attacks.
Original languageEnglish
Title of host publication2016 Euromicro Conference on Digital System Design (DSD)
EditorsParis Kitsos
Number of pages8
ISBN (Electronic)9781509028177
ISBN (Print)9781509028184
Publication statusPublished - 27 Oct 2016
Externally publishedYes
EventEuromicro Conference on Digital System Design - St. Raphael Hotel, Limassol, Cyprus
Duration: 31 Aug 20162 Sep 2016 (Link to Conference Website)


ConferenceEuromicro Conference on Digital System Design
Abbreviated titleDSD
Internet address


Dive into the research topics of 'Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications'. Together they form a unique fingerprint.

Cite this