Self-Balanced Charge Pump with Fast Lock Circuit

Xiang Jiang; Xuecheng Zou; Dingzhong Xiao; Sanqing Liu

doi:10.1007/BF02836677

Self-Balanced Charge Pump with Fast Lock Circuit

Xiang Jiang, Xuecheng Zou, Dingzhong Xiao, Sanqing Liu

Research output: Contribution to journal › Article › peer-review

Abstract

A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25 μm 1P5M complementary metal-oxide semiconductor (CMOS) process with a 2.5 V supply voltage. HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error. Incorporated fast lock circuit can shorten start-up time to below 300 ns.

Original language	English
Pages (from-to)	621-624
Number of pages	4
Journal	Wuhan University Journal of Natural Sciences
Volume	11
Issue number	3
DOIs	https://doi.org/10.1007/BF02836677
Publication status	Published - 1 May 2006
Externally published	Yes

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title = "Self-Balanced Charge Pump with Fast Lock Circuit",

abstract = "A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25 μm 1P5M complementary metal-oxide semiconductor (CMOS) process with a 2.5 V supply voltage. HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error. Incorporated fast lock circuit can shorten start-up time to below 300 ns.",

keywords = "Analog circuit, Charge pump, Phase-locked loops, Phase/frequency detector, Self-balanced",

author = "Xiang Jiang and Xuecheng Zou and Dingzhong Xiao and Sanqing Liu",

year = "2006",

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day = "1",

doi = "10.1007/BF02836677",

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T1 - Self-Balanced Charge Pump with Fast Lock Circuit

AU - Jiang, Xiang

AU - Zou, Xuecheng

AU - Xiao, Dingzhong

AU - Liu, Sanqing

PY - 2006/5/1

Y1 - 2006/5/1

N2 - A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25 μm 1P5M complementary metal-oxide semiconductor (CMOS) process with a 2.5 V supply voltage. HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error. Incorporated fast lock circuit can shorten start-up time to below 300 ns.

AB - A self-balanced charge pump (CP) with fast lock circuit to achieve nearly zero phase error is proposed and analyzed. The proposed CP is designed based on the SMIC 0.25 μm 1P5M complementary metal-oxide semiconductor (CMOS) process with a 2.5 V supply voltage. HSPICE simulation shows that even if the mismatch of phase/frequency detector (PFD) was beyond 10%, the charge pump could still keep nearly zero phase error. Incorporated fast lock circuit can shorten start-up time to below 300 ns.

KW - Analog circuit

KW - Charge pump

KW - Phase-locked loops

KW - Phase/frequency detector

KW - Self-balanced

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DO - 10.1007/BF02836677

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EP - 624

JO - Wuhan University Journal of Natural Sciences

JF - Wuhan University Journal of Natural Sciences

SN - 1007-1202

IS - 3

ER -

Self-Balanced Charge Pump with Fast Lock Circuit

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