Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks

Anju Johnson, Junxiu Liu, Alan Millard, Shvan Karim, Andy Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David Halliday

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Spike-based brain-inspired systems have shown an immense capability to achieve internal stability, widely referred to as homeostasis. This ability enrols them as the best candidate for next-generation computational neuroscience as they bridge the gap between neuroscience and machine learning. Spiking Neural Networks (SNN), a third generation Artificial Neural Network (ANN), which operates using discrete events of spikes, contributes to a category of biologically-realistic models of neurons to carry out computations. Spiking Astrocyte-Neuron Networks (SANN) have a characteristic attribute homologous to brain self-repair. Although SNNs are more powerful in theory than 2nd generation ANNs, they are not widely in use as their implementations on normal hardware are computationally-intensive. On the contrary, due to the capability of modern hardware such as FPGAs, which operates in MHz and GHz range, facilitates real-time and faster-than-real-time simulations of SNNs. In this work, we overcome the computational overhead of the SNNs using the benefits of real-time hardware computations, utilizing time-multiplexing to design a Self-rePairing spiking Astrocyte Neural NEtwoRk (SPANNER) chip, generic to users` choice of task, emphasizing fault-tolerance, targeting safety-critical applications. We demonstrate the proposed methodology on a SANN system implemented on Xilinx Artix-7 FPGA. The proposed architecture has minimal hardware footprints, power dissipation profile and real-time computational capability, enhancing its usability in constrained applications.
LanguageEnglish
Title of host publicationProceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018
EditorsSuresh Sundaram
PublisherIEEE
Pages1076-1083
Number of pages8
Volume3
ISBN (Electronic)9781538692769
ISBN (Print)9781538692776
DOIs
Publication statusPublished - 31 Jan 2019
Externally publishedYes
EventIEEE Symposium on Computational Intelligence - Bengaluru, India
Duration: 18 Nov 201821 Nov 2018
http://ieee-ssci2018.org/ (Link to Conference Website)

Conference

ConferenceIEEE Symposium on Computational Intelligence
Abbreviated titleIEEE-SSCI 2018
CountryIndia
CityBengaluru
Period18/11/1821/11/18
Internet address

Fingerprint

Neurons
Hardware
Neural networks
Field programmable gate arrays (FPGA)
Brain
Fault tolerance
Multiplexing
Learning systems
Energy dissipation
Repair
Astrocytes
System-on-chip

Cite this

Johnson, A., Liu, J., Millard, A., Karim, S., Tyrrell, A., Harkin, J., ... Halliday, D. (2019). Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks. In S. Sundaram (Ed.), Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018 (Vol. 3, pp. 1076-1083). IEEE. https://doi.org/10.1109/SSCI.2018.8628710
Johnson, Anju ; Liu, Junxiu ; Millard, Alan ; Karim, Shvan ; Tyrrell, Andy ; Harkin, Jim ; Timmis, Jon ; McDaid, Liam ; Halliday, David. / Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks. Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018. editor / Suresh Sundaram. Vol. 3 IEEE, 2019. pp. 1076-1083
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Johnson, A, Liu, J, Millard, A, Karim, S, Tyrrell, A, Harkin, J, Timmis, J, McDaid, L & Halliday, D 2019, Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks. in S Sundaram (ed.), Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018. vol. 3, IEEE, pp. 1076-1083, IEEE Symposium on Computational Intelligence, Bengaluru, India, 18/11/18. https://doi.org/10.1109/SSCI.2018.8628710

Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks. / Johnson, Anju; Liu, Junxiu; Millard, Alan; Karim, Shvan; Tyrrell, Andy ; Harkin, Jim; Timmis, Jon; McDaid, Liam; Halliday, David.

Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018. ed. / Suresh Sundaram. Vol. 3 IEEE, 2019. p. 1076-1083.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Johnson A, Liu J, Millard A, Karim S, Tyrrell A, Harkin J et al. Time-multiplexed System-on-Chip using Fault-tolerant Astrocyte-Neuron Networks. In Sundaram S, editor, Proceedings of the 2018 IEEE Symposium Series on Computational Intelligence, SSCI 2018. Vol. 3. IEEE. 2019. p. 1076-1083 https://doi.org/10.1109/SSCI.2018.8628710