Embedded Sensor Data Acquisition using Non-linear Chaos Based Systems

  • Philippa Hazell

Student thesis: Doctoral Thesis


Recent research into tent map (TM) based analogue to digital converter (ADC) architectures, has demonstrated that practical implementations are able to detect small analogue signal variations over relatively large voltage ranges. However, the non-ideal nature of the fundamental TM function slope gain (μ) affects the absolute accuracy and the digital output precision. Although there has been a successful attempt at compensating for non-ideal μ, the high levels of computational resources required makes realising embedded digital system implementations, within a TM-based ADC, unfeasible. This in turn limits the prospect of realtime operation and thus viable commercial TM-based ADC devices.

This work aimed to further develop TM-based ADC performance, to enable more precise and accurate real-time operations, within a data acquisition (DAQ) system, for an ultrasonic measurement system (UMS) application. To facilitate this, an embedded digital implementation of a real-time processing µ compensation algorithm (µCA) was required to adjust the incorrect digital output signal of a TM-based ADC implementation towards the ideal digital output response for a given analogue input signal. To aid analysis of how non-ideal μ affects the TM-based ADC output accuracy, a mathematical model of a TM-based ADC, emulating an electronic implementation operational performance, was created. A novel µCA was then developed, with further compensation for non-ideal behaviours within the electronic circuit implementations of the TM function. Additionally, a VHDL implementation (for configuring a field programmable gate array (FPGA)) enabled the embedment of a digital system performing real-time μ compensation within a TM-based ADC. This digital system was tested using functional simulation and an electronic 8-bit TM-based ADC implementation.

The mathematical model of a TM-based ADC structure, comprising 7 cascaded TM and comparator stages implemented with a 12-bit commercial off the shelf (COTS) ADC digitising the final TM stage output, demonstrated that the bit accuracy improved from 5.81 bits uncompensated, to 15.68 bits after employing the µCA. This established that the proposed TM-based ADC met the UMS DAQ system specification. With the practical implementation, which was prototyped using discrete components, a bit accuracy improvement from 4.19 bits to 5 bits was observed. Both the functional simulations and practical experiments employing the VHDL/FPGA implementation of the µCA proved the concept of a standalone TM-based ADC (comprising 7 cascaded TM and comparator stages with a comparator digitising the final TM stage output) with embedded, real-time µ compensation was achievable.
Date of Award2023
Original languageEnglish
SupervisorPeter Mather (Main Supervisor), Simon Fletcher (Co-Supervisor) & Andrew Longstaff (Co-Supervisor)

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